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HYB18TC512800BF-25F 参数 Datasheet PDF下载

HYB18TC512800BF-25F图片预览
型号: HYB18TC512800BF-25F
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 64MX8, 0.4ns, CMOS, PBGA60, GREEN, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 62 页 / 1954 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18TC512[80/16]0BF  
512-Mbit Double-Data-Rate-Two SDRAM  
2
Configuration  
This chapter contains the chip configuration, addressing and block diagrams.  
2.1  
Chip Configuration for PG-TFBGA-60  
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# and Buffer Type  
columns are explained in Table 7 and Table 8 respectively.  
TABLE 6  
Chip Configuration of DDR2 SDRAM  
Ball#  
Name  
Ball  
Type  
Buffer  
Type  
Function  
Clock Signals ×8 organization  
E8  
F8  
F2  
CK  
I
I
I
SSTL  
SSTL  
SSTL  
Clock Signal CK, CK  
Clock Enable  
CK  
CKE  
Control Signals ×8 organizations  
F7  
G7  
F3  
G8  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
CS  
Chip Select  
Address Signals ×8 organizations  
G2  
G3  
H8  
H3  
H7  
J2  
BA0  
BA1  
A0  
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
SSTL  
Bank Address Bus 1:0  
Address Signal 13:0, Address Signal 10/Autoprecharge  
A1  
A2  
A3  
J8  
A4  
J3  
A5  
J7  
A6  
K2  
K8  
K3  
H2  
A7  
A8  
A9  
A10  
AP  
A11  
A12  
A13  
K7  
L2  
L8  
Rev. 1.21, 2007-09  
6
03292006-HDLH-OAY6