6
W'+ꢌꢌ
W'6ꢌꢌ
''4ꢌꢌ
9ꢌ,+ꢌ ꢎDF ꢌPL
Q
Q
ꢌꢌ
ꢌꢌ
ꢏꢌꢌ
9ꢌ,+ꢌ ꢎGF ꢌPL
ꢏꢌꢌ
9ꢌꢌ F ꢌPD
[
[
ꢌꢌ
ꢌꢌ
,/ꢎ
G ꢏꢌꢌ
9ꢌꢌ F ꢌPD
,/ꢎ
D ꢏꢌꢌ
Internet Data Sheet
HYB18TC512[80/16]0BF
512-Mbit Double-Data-Rate-Two SDRAM
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
34) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
35) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 5
Method for calculating transitions and endpoint
6/( ꢂ X M6
644 ꢃ ꢁX M6
6/( ꢂ ꢁX M6
644 ꢃ X M6
T,:
T(:
T202% BEGIN POINT
T2034 END POINT
6/, ꢃ ꢁX M6
6/, ꢃ X M6
644 ꢂ X M6
644 ꢂ ꢁX M6
4ꢀ 4ꢁ
T,:ꢄT202% BEGIN POINT ꢅ ꢁꢆ4ꢀꢂ4ꢁ
4ꢀ 4ꢁ
T(:ꢄT2034 END POINT ꢅ ꢁꢆ4ꢀꢂ4ꢁ
FIGURE 6
Differential input waveform timing - tDS and tDH
'46ꢌꢌ
'4 ꢌꢌ
W'+ꢌꢌ
W'6ꢌꢌ
9ꢌꢌ
9ꢌꢌ
5()ꢎGFꢏꢌꢌ
9ꢌꢌ
66ꢌꢌ
0377ꢈꢆꢊꢀ
Rev. 1.21, 2007-09
03292006-HDLH-OAY6
43
QIMONDA [ QIMONDA AG ]
