Internet Data Sheet
HYB18TC256[80/16]0BF
256-Mbit Double-Data-Rate-Two SDRAM
2.2
Chip Configuration for PG-TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Ball# columns are
explained in Table 7 and Table 8 respectively.
TABLE 9
Chip Configuration of DDR SDRAM
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×16 Organization
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
K8
K2
CK
CKE
Control Signals ×16 Organization
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
CS
Chip Select
Address Signals ×16 Organization
L2
BA0
BA1
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 1:0
L3
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
Address Signal 12:0,Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
P7
R2
Rev. 1.3, 2007-05
10
07182006-DD60-22E6
QIMONDA [ QIMONDA AG ]
