Internet Data Sheet
HY[B/I]18TC256[80/16]0AF
256-Mbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3S
–3.7
–5
Unit
DRAM Speed Grade
CAS-RCD-RP latencies
DDR2
–800D
5–5–5
–800E
6–6–6
–667D
5–5–5
–533C
4–4–4
–400B
3–3–3
tCK
Max.
Clock Frequency
CL3
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
200
266
400
–
200
266
333
400
15
200
266
333
–
200
266
266
–
200
200
–
MHz
MHz
MHz
MHz
ns
CL4
CL5
CL6
–
Min. RAS-CAS-Delay
12.5
12.5
45
15
15
15
15
40
55
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
15
15
ns
tRAS
tRC
45
45
45
ns
57.5
60
60
60
ns
1.2
Description
The 256-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing
268,435,456 bits and internally configured as a quad-bank
DRAM. The 256-Mbit device is organized as 8 Mbit ×8 I/O ×4
banks or 4 Mbit ×16 I/O ×4 banks chip.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
A 15 bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The device is designed to comply with all DDR2 DRAM key
features:
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
The DDR2 SDRAM is available in TFBGA package.
Rev. 1.3, 2007-11
4
03062006-H3V1-XJT4
Date: 2007-11-23
QIMONDA [ QIMONDA AG ]
