Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
TABLE 38
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
Unit
Note
IFX Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
tCK
Parameter
Symbol
Min.
Max.
—
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
tCK
5
8
ns
ns
ns
ns
ns
ns
ns
tCK
3.75
3.75
45
8
tCK
8
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
tRAS
tRC
tRCD
tRP
70000
—
60
15
—
15
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) under the “Reference Load for Timing Measurements”.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode; The input reference level for signals other than CK/CK, DQS / DQS,
RDQS / RDQS is defined.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT
.
5) RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI
t
.
Rev. 1.11, 2006-09
35
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
