Internet Data Sheet
HYB18TC1G[80/16]0AF
1-Gbit DDR2 SDRAM
Field
Bits
Type1)
Description
A13
13
w
Address Bus[13]
Note: A13 is not available for 256 Mbit and ×16 512 Mbit configuration
0B A13 Address bit 13
Output Disable
Qoff
12
0B
1B
QOff Output buffers enabled
QOff Output buffers disabled
RDQS
DQS
11
Read Data Strobe Output (RDQS, RDQS)
0B
1B
RDQS Disable
RDQS Enable
10
Complement Data Strobe (DQS Output)
0B
1B
DQS Enable
DQS Disable
OCD
Program
[9:7]
Off-Chip Driver Calibration Program
000B OCD OCD calibration mode exit, maintain setting
001B OCD Drive (1)
010B OCD Drive (0)
100B OCD Adjust mode
111B OCD OCD calibration default
AL
[5:3]
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
RTT
6,2
Nominal Termination Resistance of ODT
Note: See Table 23 “ODT DC Electrical Characteristics” on Page 24
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
Rev. 1.11, 2006-09
16
03292006-PJAE-UQLG
QIMONDA [ QIMONDA AG ]
