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HYB18T512400B2FL-25F 参数 Datasheet PDF下载

HYB18T512400B2FL-25F图片预览
型号: HYB18T512400B2FL-25F
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 128MX4, 0.4ns, CMOS, PBGA60, GREEN, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 66 页 / 3789 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T512[40/80/16]0B2[C/F](L)  
512-Mbit Double-Data-Rate-Two SDRAM  
Parameter  
Symbol  
DDR2–533  
DDR2–400  
Unit  
Notes1)2)  
3)4)5)6)  
Min.  
Max.  
Min.  
Max.  
13)  
13)  
DQ low-impedance time from CK / tLZ.DQ  
CK  
2 × tAC.MIN  
tAC.MAX  
2 × tAC.MIN  
tAC.MAX  
ps  
ps  
ns  
tCK  
DQS/DQS low-impedance time from tLZ.DQS  
CK / CK  
tAC.MIN  
tAC.MAX  
12  
tAC.MIN  
tAC.MAX  
12  
MRS command to ODT update  
delay  
tMOD  
tMRD  
0
2
0
0
2
0
Mode register set command cycle  
time  
OCD drive mode output delay  
Data output hold time from DQS  
Data hold skew factor  
tOIT  
12  
12  
ns  
ps  
ps  
μs  
μs  
ns  
tQH  
t
HP tQHS  
t
HP tQHS  
tQHS  
tREFI  
tREFI  
tRFC  
400  
7.8  
3.9  
450  
7.8  
3.9  
13)14)  
15)17)  
16)  
Average periodic refresh Interval  
Average periodic refresh Interval  
Auto-Refresh to Active/Auto-  
Refresh command period  
105  
105  
13)  
Read preamble  
Read postamble  
tRPRE  
tRPST  
tRRD  
0.9  
1.1  
0.60  
0.9  
1.1  
0.60  
tCK  
tCK  
ns  
13)  
0.40  
7.5  
0.40  
7.5  
13)17)  
Active bank A to Active bank B  
command period for 1 KB page size  
15)21)  
Active bank A to Active bank B  
command period for 2 KB page size  
tRRD  
10  
10  
ns  
ns  
Internal Read to Precharge  
command delay  
tRTP  
7.5  
7.5  
Write preamble  
tWPRE  
tWPST  
tWR  
0.35  
0.40  
15  
0.35  
0.40  
15  
tCK  
tCK  
ns  
ns  
18)  
Write postamble  
Write recovery time  
0.60  
0.60  
19)  
20)  
20)  
Internal Write to Read command  
delay  
tWTR  
7.5  
10  
Exit active power down to read  
command  
tXARD  
2
2
tCK  
tCK  
tCK  
ns  
Exit active power down to read  
command (slow exit, lower power)  
tXARDS  
6 – AL  
2
6 – AL  
2
Exit precharge power down to any tXP  
non-read command  
Exit Self-Refresh to non-read  
command  
tXSNR  
t
RFC +10  
tRFC +10  
Exit Self-Refresh to Read command tXSRD  
200  
WR/tCK  
200  
WR/tCK  
tCK  
tCK  
21)  
Write recovery time for write with  
Auto-Precharge  
WR  
t
t
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.  
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
Rev. 1.40, 2008-03  
48  
10062006-YPTZ-CDR7  
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