Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 39
DRAM Component Timing Parameter by Speed Grade - DDR2–533 and DDR2–400
Parameter
Symbol
DDR2–533
DDR2–400
Unit
Notes1)2)
3)4)5)6)
Min.
Max.
Min.
Max.
DQ output access time from CK / CK tAC
–500
2
+500
—
–600
2
+600
—
ps
CAS to CAS command delay
CK high pulse width
tCCD
tCK
tCK
tCK
tCH
0.45
3
0.55
—
0.45
3
0.55
—
CKE minimum high and low pulse
width
tCKE
CK low pulse width
tCL
0.45
0.55
—
0.45
0.55
—
tCK
tCK
7)
8)
Auto-Precharge write recovery +
precharge time
tDAL
WR + tRP
WR + tRP
Minimum time clocks remain ON
after CKE asynchronously drops
LOW
tDELAY
tIS + tCK + tIH ––
tIS + tCK + tIH ––
ns
9)
DQ and DM input hold time
(differential data strobe)
tDH.BASE
225
––
275
25
––
ps
ps
tCK
ps
10)
DQ and DM input hold time (single tDH1.BASE
ended data strobe)
–25
—
—
DQ and DM input pulse width for
each input
tDIPW
0.35
–450
—
0.35
–500
—
DQS output access time from CK / tDQSCK
+450
+500
CK
DQS input HIGH pulse width
DQS input LOW pulse width
tDQSH
tDQSL
tDQSQ
0.35
0.35
—
—
0.35
0.35
—
—
tCK
tCK
ps
—
—
10)
DQS-DQ skew (for DQS &
associated DQ signals)
300
350
DQS latching rising transition to
associated clock edges
tDQSS
– 0.25
100
+ 0.25
—
– 0.25
150
+ 0.25
—
tCK
ps
ps
10)
10)
DQ and DM input setup time
(differential strobe)
tDS.BASE
DQ and DM input setup time (single tDS1.BASE
–25
—
25
—
ended strobe)
DQS falling edge hold time from CK tDSH
DQS falling edge to CK setup time tDSS
0.2
—
—
__
0.2
—
—
__
tCK
tCK
ps
0.2
0.2
11)
12)
10)
CK half pulse width
tHP
Min(tCH.ABS
tCL.ABS
,
Min(tCH.ABS,
tCL.ABS)
)
Data-out high-impedance time from tHZ
CK / CK
—
tAC.MAX
—
tAC.MAX
ps
Address and control input hold time tIH.BASE
375
0.6
—
—
475
0.6
—
—
ps
Address and control input pulse
width for each input
tIPW
tCK
10)
Address and control input setup time tIS.BASE
250
—
350
—
ps
Rev. 1.40, 2008-03
47
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
