Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
Field
Bits Type1)
[5:3] w
Description
AL
Additive Latency
Note: All other bit combinations are illegal.
000B AL 0
001B AL 1
010B AL 2
011B AL 3
100B AL 4
101B AL 5
110B AL 6
RTT
6,2
w
Nominal Termination Resistance of ODT
Note: See Table 22 “ODT DC Electrical Characteristics” on Page 30
00B RTT ∞ (ODT disabled)
01B RTT 75 Ohm
10B RTT 150 Ohm
11B RTT 50 Ohm
DIC
DLL
1
0
w
w
Off-chip Driver Impedance Control
0B
1B
DIC Full (Driver Size = 100%)
DIC Reduced
DLL Enable
0B
1B
DLL Enable
DLL Disable
1) w = write only register bits
Rev. 1.40, 2008-03
23
10062006-YPTZ-CDR7
QIMONDA [ QIMONDA AG ]
