Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
FIGURE 1
Configuration for ×4 Components, TFBGA-60 (top view)
ꢃ
ꢆ
ꢅ
ꢉ
ꢇ
ꢁ
ꢂ
ꢊ
ꢈ
$
9''
966
9664
9''4
1&
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9664
9664
%
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(
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+
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9''4
9''4
9''4
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9664
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.
/
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9''
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0337ꢀꢁꢂꢀ
Note: VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and
SSQ are isolated on the device.
V
Rev. 1.40, 2008-03
12
10062006-YPTZ-CDR7