Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–400
Unit
Note
1)2)3)4)5)6)7)
Min.
Max.
11)
DQ and DM input setup time (single ended
data strobe)
t
DS1(base)
–25
—
ps
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
—
—
tCK
ns
ns
—
Four Activate Window period
Four Activate Window period
Clock half period
tFAW
tFAW
tHP
37.5
13)
12)
13)
11)
50
MIN. (tCL, tCH
)
Data-out high-impedance time from CK / CK
Address and control input hold time
tHZ
—
tAC.MAX
—
ps
ps
tCK
tIH(base)
tIPW
475
0.6
Address and control input pulse width
(each input)
—
11)
14)
14)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
350
—
ps
ps
ps
tCK
ns
—
ps
µs
µs
ns
2 × tAC.MIN
tAC.MAX
tAC.MAX
—
tAC.MIN
2
0
tOIT
12
Data output hold time from DQS
Data hold skew factor
tQH
t
HP –tQHS
—
tQHS
—
450
7.8
14)15)
16)18)
17)
Average periodic refresh Interval
Average periodic refresh Interval
tREFI
—
tREFI
—
3.9
Auto-Refresh to Active/Auto-Refresh
command period
127.5
—
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
tRP
t
RP + 1tCK
—
ns
ns
tCK
tCK
ns
tRP
15 + 1tCK
0.9
—
14)
tRPRE
tRPST
tRRD
1.1
0.60
—
14)
Read postamble
0.40
14)18)
Active bank A to Active bank B command
period
7.5
16)22)
Active bank A to Active bank B command
period
tRRD
10
—
ns
Internal Read to Precharge command delay
Write preamble
tRTP
7.5
—
ns
tCK
tCK
ns
tWPRE
tWPST
tWR
0.25
0.40
15
—
19)
Write postamble
0.60
—
Write recovery time for write without Auto-
Precharge
20)
21)
Internal Write to Read command delay
tWTR
10
2
—
—
ns
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
Rev. 1.2, 2007-01
24
03292006-AYVF-ZIIJ
QIMONDA [ QIMONDA AG ]
