5(ꢄꢄEHJLꢄQꢄSRLQWꢄ
7
ꢄ
Hꢄ
ꢄSRLꢄQW
ꢄ
92/
ꢄꢍꢄꢈ[ꢄP9
ꢄꢍꢄ[ꢄP9
ꢄ
977ꢄꢃꢄ[ꢄP
9ꢄ
92/
ꢄ
977ꢄꢃꢄꢈ[ꢄP9ꢄ
7ꢁꢄ 7ꢈꢄ
W+=ꢎW536
7ꢄꢄHQG
ꢄSRLQ
Wꢄꢄ
ꢄꢈꢏ
7ꢁꢃ7ꢈꢄ
W/=ꢎW
535(ꢄEꢄ
Wꢄꢄ
ꢄꢈꢏ7
ꢁꢃ7ꢈꢄ
'46ꢄ
W'+ꢄ
W'6ꢄ
ꢄ
9,ꢄ+ꢐDFꢑꢄꢄPLQ
9,ꢄ+ꢐGFꢑꢄꢄPLQ
95ꢄ ()ꢐGFꢑꢄ
ꢄ
ꢄ
9,ꢄ/ꢐGFꢑꢄꢄPD[
9,ꢄ/ꢐDFꢑꢄꢄPD[
96ꢄ 6ꢄ
ꢄ
ꢄ
W,+ꢄ
W,+
ꢄ
W,6ꢄ
W,6ꢄ
ꢄ
ꢑꢄ
ꢑꢄ
9,ꢄ/ꢐGF ꢄPD[
ꢄ
ꢄ
ꢑꢄ
9,ꢄ/ꢐDF ꢄPD[
ꢑꢄ
Internet Data Sheet
HYS72T[512/256]02xHR–[3S/3.7/5]–A
Registered DDR2 SDRAM Modules
32) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
92+
ꢄꢃꢄ[ꢄP9
ꢄ
977ꢄꢍꢄꢈ[ꢄP9ꢄ
977ꢄꢍꢄ[ꢄP9ꢄ
92+
ꢄꢃꢄꢈ[ꢄP9ꢄ
W/=ꢄ
W53
W+=ꢄ
W536 QG
7ꢁꢄ 7ꢈꢄ
HJLQꢄSRLQ
FIGURE 3
Differential input waveform timing - tDS and tDS
'46ꢄ
W'+ꢄ
W'6ꢄ
9'ꢄ '4
FIGURE 4
Differential input waveform timing - tlS and tlH
&.ꢄ
&.ꢄ
9'ꢄ '4
9,ꢄ+ꢐDF ꢄPLQꢄ
9,ꢄ+ꢐGF ꢄPLQꢄ
95ꢄ ()ꢐGFꢑꢄ
96ꢄ 6ꢄ
Rev. 1.2, 2007-01
20
03292006-AYVF-ZIIJ
QIMONDA [ QIMONDA AG ]
