Internet Data Sheet
HYS72T1G242EP–[25F/2.5/3/3S/3.7]–C
Registerd DDR2 SDRAM Module
1.2
Description
The Qimonda HYS72T1G242EP–[25F/2.5/3//3S/3.7]–C module
family are Registered DIMM (with parity) modules with 30 mm
height based on DDR2 technology.
distribution. This reduces capacitive loading to the system
bus, but adds one cycle to the SDRAM timing. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
DIMMs are available as ECC modules in 1024M × 72 (8 GB)
organization and density, intended for mounting into 240-Pin
connector sockets.
The memory array is designed with stacked 2 Gbit (1Gbit
Dual Dies) Double-Data-Rate-Two (DDR2) Synchronous
DRAMs. All control and address signals are re-driven on the
DIMM using register devices and a PLL for the clock
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
PC2–6400
HYS72T1G242EP-2.5-C
HYS72T1G242EP-25F-C
PC2–5300
8GB 4Rx4 PC2-6400P-666-12-ZZ
8GB 4Rx4 PC2-6400P-555-12-ZZ
4 Rank, ECC
4 Rank, ECC
1Gbit (× 4)
1Gbit (× 4)
HYS72T1G242EP-3-C
HYS72T1G242EP-3S-C
PC2–4200
8GB 4Rx4 PC2-5300P-444-12-ZZ
8GB 4Rx4 PC2-5300P-555-12-ZZ
4 Rank, ECC
4 Rank, ECC
1Gbit (× 4)
1Gbit (× 4)
HYS72T1G242EP-3.7-C
8GB 4Rx4 PC2-4200P-444-12-ZZ
4 Rank, ECC
1Gbit (× 4)
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T1G242EP-3.7-C, indicating Rev.
“C” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200P–444–12–ZZ”, where 4200P
means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe
(CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2
and produced on the Raw Card “F”
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
8 GByte
1024M ×72
4
ECC
36DDP1)
14/3/11
Z
1) DDP Dual Die Package
TABLE 4
Components on Modules
DRAM Organization
2 × 512M × 4
Product Type1)
DRAM Components
DRAM Density
HYS72T1G242EP
HYB18T2G402CF
1 Gbit
1) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.0, 2007-07
4
07242007-LR08-OZC0
QIMONDA [ QIMONDA AG ]
