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HYB18T1G400C2C-3 参数 Datasheet PDF下载

HYB18T1G400C2C-3图片预览
型号: HYB18T1G400C2C-3
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA60, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 68 页 / 3874 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HY[B/I]18T1G[40/80/16]0C2[C/F]  
1-Gbit Double-Data-Rate-Two SDRAM  
2
Configuration  
This chapter contains the chip configuration.  
2.1  
Configuration for TFBGA-60  
The chip configuration of a DDR2 SDRAM is listed by function in Table 4. The abbreviations used in the Ball# and BufferType  
column are explained in Table 5 and Table 6 respectively.  
TABLE 4  
Chip Configuration  
Ball#  
Name  
Ball  
Type  
Buffer  
Type  
Function  
Clock Signals ×4/×8 Organizations  
E8  
F8  
F2  
K2  
CK  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Clock Signal CK, CK  
CK  
CKE  
CKE  
Clock Enable  
Clock Enable  
Control Signals ×4/×8 Organizations  
F7  
G7  
F3  
G8  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
CS  
Chip Select  
Address Signals ×4/×8 Organizations  
G2  
G3  
G1  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 2:0  
Rev. 1.02, 2008-01  
8
09262007-3YK7-BKKG