Internet Data Sheet
HY[B/I]18T1G[40/80/16]0C2[C/F]
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
–1.9
–25F
–2.5
–3
–3S
–3.7
–5
Unit
DRAM Speed Grade
CAS-RCD-RP latencies
DDR2 –1066F
–800D
5–5–5
–800E
6–6–6
–667C
4–4–4
–667D
5–5–5
–533C
4–4–4
–400B
3–3–3
7–7–7
tCK
Max.
Clock Frequency
CL3 fCK3
–
200
266
400
–
200
266
333
400
–
200
333
333
–
200
266
333
–
200
266
266
–
200
200
–
MHz
MHz
MHz
MHz
MHz
ns
CL4 fCK4
266
CL5 fCK5
CL6 fCK6
CL7 fCK7
333
400
–
533
–
–
–
–
–
Min. RAS-CAS-Delay
tRCD
tRP
13.125
13.125
12.5
12.5
15
12
12
15
15
15
15
15
15
Min. Row Precharge
Time
15
ns
Min. Row Active Time
Min. Row Cycle Time
tRAS
tRC
45
45
45
45
57
15
45
60
18
45
40
55
20
ns
ns
ns
58.125
15
57.5
15
60
60
Precharge-All (8 banks) tPREA
17.5
18.75
command period
1.2
Description
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device containing
1,073,741,824 bits and internally configured as an octal bank
DRAM.
The 1-Gbit device is organized as 32 Mbit ×4 I/O ×8 banks or
16 Mbit ×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
A 17 bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The device is designed to comply with all DDR2 DRAM key
features:
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
Rev. 1.02, 2008-01
4
09262007-3YK7-BKKG