HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Pin Configuration
Table 4
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
A13
P7
R2
R8
Address Signal 13
Note: x4/x8 1 Gbit components
Note: x16 1 Gbit components
NC
–
–
Address Signals ×16 organization
P2
P3
P1
R8
R3
R7
T2
T8
T3
T7
U2
U8
U3
R2
BA0
BA1
BA2
A0
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Address Signal 12:0, Address Signal 10/Autoprecharge
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
AP
A11
A12
U7
V2
Data Signals ×4/×8 organizations
G8
G2
H7
H3
DQ0
DQ1
DQ2
DQ3
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
Data Signal 3:0
Note: Bi-directional data bus. DQ[3:0] for ×4 components, DQ[7:0]
for ×8 components
Internet Data Sheet
7
Rev. 1.31, 2007-01
03292006-1X3H-6X8S