HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Pin Configuration
2
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 4. The abbreviations used in the Pin# and
Buffer Type columns are explained in Table 5 and Table 6 respectively. The pin numbering for the FBGA package
is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Table 4
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8 organizations
J8
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Clock Enable
K8
K2
CK
CKE
Clock Signals ×16 organization
M8
N8
N2
CK
I
I
I
SSTL
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: See functional description in x4/x8 organization
Clock Enable
CK
CKE
Note: See functional description in x4/x8 organization
Control Signals ×4/×8 organizations
K7
L7
K3
L8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Control Signals ×16 organization
N7
P7
N3
P8
RAS
CAS
WE
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS
Chip Select
Address Signals ×4/×8 organizations
L2
L3
L1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Internet Data Sheet
6
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
