HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration for ×4 components, PG-TFBGA-68 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Pin Configuration for ×8 components, PG-TFBGA-68 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Pin Configuration for ×16 components, P-TFBGA-92 (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Single-ended AC Input Test Conditions Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . 30
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins. . . . . . . . . . . . . . . . 31
Package Pinout PG-TFBGA-68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package Pinout PG-TFBGA-92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Internet Data Sheet
50
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
