HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Operating Conditions
5.4
Output Buffer Characteristics
Table 25
Symbol
IOH
SSTL_18 Output DC Current Drive
Parameter
SSTL_18
–13.4
Unit
mA
Note
1)2)
Output Minimum Source DC Current
Output Minimum Sink DC Current
3)
IOL
13.4
mA
1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and
DDQ – 280 mV.
V
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in and . They are used to test drive current capability to
ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Table 26
Symbol
VOH
SSTL_18 Output AC Test Conditions
Parameter
SSTL_18
Unit
V
Note
1)
Minimum Required Output Pull-up
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
VOL
V
VOTR
V
1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series
resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be
developed across the effectively 25 Ohm termination resistor (13.4 mA x 25 Ohm = 335 mV). With an additional series
resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4
mA x 45 Ohm = 603 mV).
Internet Data Sheet
28
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
