HYB18T1G[40/80/16]0AF(L)–[3S/3.7/5]
1-Gbit DDR2 SDRAM
Operating Conditions
Table 24
Symbol
VIN(dc)
Differential DC and AC Input and Output Logic Levels
Parameter
Min.
Max.
Unit
—
—
V
Note
1)
DC input signal voltage
DC differential input voltage
AC differential input voltage
–0.3
V
V
V
DDQ + 0.3
2)
3)
4)
VID(dc)
0.25
DDQ + 0.6
DDQ + 0.6
VID(ac)
0.5
VIX(ac)
AC differential cross point input
voltage
0.5 × VDDQ – 0.175
0.5 × VDDQ + 0.175
V
5)
VOX(ac)
AC differential cross point output
voltage
0.5 × VDDQ – 0.125
0.5 × VDDQ + 0.125
V
1) VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
2) VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc)
3) VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac)
4) The value of VIX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VIX(ac) is expected to track variations in
.
.
V
DDQ. VIX(ac) indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 x VDDQ of the transmitting device and VOX(ac) is expected to track variations in
V
DDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
VDDQ
VTR
Crossing Point
VID
VIX or VOX
VCP
VSSQ
SSTL18_3
Figure 5
Differential DC and AC Input and Output Logic Levels Diagram
Internet Data Sheet
27
Rev. 1.31, 2007-01
03292006-1X3H-6X8S
QIMONDA [ QIMONDA AG ]
