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HYB18T1G160C4F-25F 参数 Datasheet PDF下载

HYB18T1G160C4F-25F图片预览
型号: HYB18T1G160C4F-25F
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 64MX16, 0.4ns, CMOS, PBGA84, GREEN, PLASTIC, TFBGA-84]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 58 页 / 1898 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB18T1G[40/80/16]0C4F  
1-Gbit Double-Data-Rate-Two SDRAM  
Parameter  
Symbol DDR2–800  
Min.  
DDR2–667  
Min.  
Unit  
Note1)2)3  
)4)5)6)7)  
Max.  
Max.  
8)21)  
8)21)  
DQ low impedance time from CK/CK tLZ.DQ  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
2 × tAC.MIN  
tAC.MAX  
tAC.MAX  
ps  
ps  
DQS/DQS low-impedance time from tLZ.DQS  
tAC.MIN  
tAC.MIN  
CK / CK  
34)  
MRS command to ODT update delay tMOD  
0
2
12  
0
2
12  
ns  
Mode register set command cycle  
time  
tMRD  
nCK  
34)  
OCD drive mode output delay  
tOIT  
0
12  
0
12  
ns  
ps  
ps  
μs  
μs  
ns  
25)  
DQ/DQS output hold time from DQS tQH  
tHP tQHS  
t
HP tQHS  
26)  
DQ hold skew factor  
tQHS  
tREFI  
300  
7.8  
3.9  
340  
7.8  
3.9  
27)28)  
27)29)  
30)  
Average periodic refresh Interval  
Auto-Refresh to Active/Auto-Refresh tRFC  
127.5  
127.5  
command period  
31)32)  
31)33)  
34)  
Read preamble  
Read postamble  
tRPRE  
tRPST  
0.9  
0.4  
7.5  
1.1  
0.6  
0.9  
0.4  
7.5  
1.1  
0.6  
tCK.AVG  
tCK.AVG  
ns  
Active to active command period for tRRD  
1KB page size products  
34)  
34)  
Active to active command period for tRRD  
2KB page size products  
10  
10  
ns  
ns  
Internal Read to Precharge command tRTP  
7.5  
7.5  
delay  
Write preamble  
tWPRE  
tWPST  
tWR  
0.35  
0.4  
15  
0.6  
0.35  
0.4  
15  
0.6  
tCK.AVG  
tCK.AVG  
ns  
Write postamble  
Write recovery time  
34)  
34)35)  
Internal write to read command delay tWTR  
7.5  
2
7.5  
2
ns  
Exit active power down to read  
command  
tXARD  
tXARDS  
tXP  
nCK  
Exit active power down to read  
command (slow exit, lower power)  
8 – AL  
2
7 – AL  
2
nCK  
nCK  
ns  
Exit precharge power-down to any  
command  
34)  
Exit self-refresh to a non-read  
command  
tXSNR  
tRFC +10  
tRFC +10  
Exit self-refresh to read command  
tXSRD  
200  
200  
nCK  
nCK  
Write command to DQS associated  
clock edges  
WL  
RL – 1  
RL–1  
1) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.  
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down  
and then restarted through the specified initialization sequence before normal operation can continue.  
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew  
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.  
Rev. 1.01, 2008-11  
42  
04212008-66HT-ZLFE  
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