Internet Data Sheet
HYB18T1G[40/80/16]0C4F
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 3
Chip Configuration for x16 Components in FBGA–84, Top View
ꢃ
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ꢅ
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ꢂ
$
%
&
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(
)
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Notes
1. UDQS/UDQS is data strobe for DQ[15:8], LDQS/LDQS is data strobe for DQ[7:0]
2. LDM is the data mask signal for DQ[7:0], UDM is the data mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VDD, VDDQ, VSSDL, VSS, and VSSQ
are isolated on the device.
Rev. 1.01, 2008-11
16
04212008-66HT-ZLFE
QIMONDA [ QIMONDA AG ]
