Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
1.3
Description
The HY[B/E]18M256[16/32]0CF is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is
internally configured as a quad-bank DRAM.
The HY[B/E]18M256[16/32]0CF uses a double-data-rate architecture to achieve high-speed operation. The double-data-rate
architecture is essentially a 2n pre fetch architecture, with an interface designed to transfer two or four data words per clock
cycle at the I/O pins. A single READ or WRITE access for the HY[B/E]18M256[16/32]0CF consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the
I/O pins.
The HY[B/E]18M256[16/32]0CF is especially designed for mobile applications. It operates from a 1.8V power supply. Power
consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced
by using the programmable Partial Array Self Refresh (PASR).
A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power-Down (DPD)
mode. For further power-savings the clock may be stopped during idle periods.
The HY[B/E]18M256[16/32]0CF is housed in a BGA package. It is available in Standard (-0°C to +70°C) and Extended (-25°C
to +85°C) temperature ranges.
Rev.1.44, 2007-07
6
06262007-JK8G-48BV
QIMONDA [ QIMONDA AG ]
