Internet Data Sheet
HY[B/E]18M256[16/32]0CF
256-Mbit DDR Mobile-RAM
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Overview
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Features
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Organization:
– 4 banks × 4 Mbit × 16, 1 KB page size
– 4 banks × 2 Mbit × 32, 2 KB page size
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Double-data-rate architecture: two data transfers per clock cycle
Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver
DQS is edge-aligned with data for READs and center-aligned with data for WRITEs
Differential clock input (CK / CK)
Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS
Four internal banks for concurrent operation
Programmable CAS latency: 2 and 3
Programmable burst length: 2, 4, 8, 16 and full page
Programmable drive strength: full, 1/2, 1/4 and 1/8
Auto refresh and self refresh modes
Refresh cycles:
– 8192 refresh cycles / 64ms (x16)
– 4096 refresh cycles / 64ms (x32)
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Auto precharge
Commercial (-0°C to +70°C) and Extended (-25°C to +85°C) operating temperature ranges
Package:
– x16: 60–ball PG-VFBGA-60-4 10.0 × 10.5 × 1.0 mm
– x32: 90–ball PG-VFBGA-60-3 10.0 × 12.5 × 1.0 mm
RoHS Compliant Products1)
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Power Saving Features
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Low supply voltages: VDD = 1.70 V − 1.95 V, VDDQ = 1.70 V − 1.95 V
Optimized operating (IDD0, IDD4), self refresh (IDD6) and standby currents (IDD2, IDD3
DDR I/O scheme with no DLL
Programmable Partial Array Self Refresh (PASR)
Temperature Compensated Self-Refresh (TCSR), controlled by on-chip temperature sensor
Clock Stop, Power-Down and Deep Power-Down modes
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1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev.1.44, 2007-07
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06262007-JK8G-48BV
QIMONDA [ QIMONDA AG ]
