HY[B/E]18L256160B[C/F]X-7.5
256-Mbit Mobile-RAM
Functional Description
2.4.6
WRITE
WRITE bursts are initiated with a WRITE command, as
shown in Figure 23. Basic timings for the DQs are
shown in Figure 24; they apply to all write operations.
The starting column and bank addresses are provided
with the WRITE command, and Auto Precharge is
either enabled or disabled for that access. If Auto
Precharge is enabled, the row being accessed is
precharged at the completion of the write burst. For the
generic WRITE commands used in the following
illustrations, Auto Precharge is disabled.
#,+
#+%
#3
ꢌ(IGHꢍ
2!3
#!3
7%
!ꢂꢎ!ꢅ
#!
%NABLE !0
"! ꢒ "ANK ! RESS
#! ꢒ #OLUMN ! RESS
!0 ꢒ !UTO 0RECHARGE
!ꢀꢂ
!0
$ISABLE !0
ꢒ $ONgT #ARE
"!ꢂꢏ"!ꢀ
"!
Figure 23 WRITE Command
#,+
$1-
$1
T)(
T)3
T)(
T)3
$) N
$) Nꢔꢁ
ꢒ $ONgT #ARE
Figure 24 Basic WRITE Timing Parameters for DQs
During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command, and
subsequent data elements are registered on each successive positive edge of CLK. Upon completion of a burst,
assuming no other commands have been initiated, the DQs remain in High-Z state, and any additional input data
is ignored.
Figure 25 and Figure 26 show a single WRITE burst for each supported CAS latency setting.
Data Sheet
24
Rev. 1.11, 2007-01
07142005-CR47-RB2E
QIMONDA [ QIMONDA AG ]
