Internet Data Sheet
HYB18H512321BF
512-Mbit GDDR3
Ball
Type
Detailed Function
BA<0:2>
Input
Bank Address Inputs:
BA select to which internal bank an ACTIVATE, READ, WRITE or PRECHARGE command is being
applied. BA are also used to distinguish between the MODE REGISTER SET and EXTENDED
MODE REGISTER SET commands.
A<0:11>
Input
Address Inputs:
During ACTIVATE, A0-A11 defines the row address. For READ/WRITE, A2-A7 and A9 defines the
column address, and A8 defines the auto precharge bit. If A8 is HIGH, the accessed bank is
precharged after execution of the column access. If A8 is LOW, AUTO PRECHARGE is disabled and
the bank remains active. Sampled with PRECHARGE, A8 determines whether one bank is
precharged (selected by BA<0:2>, A8 LOW) or all 8 banks are precharged (A8 HIGH). During
(EXTENDED) MODE REGISTER SET the address inputs define the register settings. A<0:11> are
sampled with the positive edge of CLK.
ZQ
-
ODT Impedance Reference:
The ZQ ball is used to control the ODT impedance.
RESET
Input
Reset pin:
The RES pin is a VDDQ CMOS input. RES is not internally terminated. When RES is at LOW state the
chip goes into full reset. The chip stays in full reset until RES goes to HIGH state. The Low to High
transition of the RES signal is used to latch the CKE value to set the value of the termination resistors
of the address and command inputs. After exiting the full reset a complete initialization is required
since the full reset sets the internal settings to default.
MF
Input
Input
Mirror function pin:
The MF pin is a VDDQ CMOS input. This pin must be hardwired on board either to a power or to a
ground plane. With MF set to HIGH, the command and address pins are reassigned in order to allow
for an easier routing on board for a back to back memory arrangement.
SEN
Enables Boundary Scan Functionality:
No Boundary Scan support. This pin should be connected to GND.
VREF
Supply Voltage Reference:
VREF is the reference voltage input.
Supply Power Supply:
Power and Ground for the internal logic.
Supply I/O Power Supply:
Isolated Power and Ground for the output buffers to provide improved noise immunity.
V
V
DD, VSS
DDQ, VSSQ
NC, RFU
-
Please do not connect. Reserved for Future Use balls.
2.2
Mirror Function
The GDDR3 Graphics RAM provides a ball mirroring feature that is enabled by applying a logic HIGH on ball MF. This function
allows for efficient routing in a clam shell configuration.
Depending of the logic state applied on MF, the command and address signals will be assigned to different balls. The default
ball configuration (see Figure 2) corresponds to MF = LOW.
The DC level (HIGH or LOW) must be applied on the MF pin at power up and is not allowed to change after that.
Table 3 shows the ball assignment as a function of the logic state applied on MF.
Rev. 1.3, 2007-12
7
05292007-WAU2-UU95
QIMONDA [ QIMONDA AG ]
