Internet Data Sheet
HYB18H256321BF
256-Mbit GDDR3
4.4
Differential Clock DC and AC Levels
TABLE 12
Differential Clock DC and AC Input conditions (0 °C ≤ Tc ≤ 85 °C)
Parameter
Symbol
Limit Values
Max.
Unit Note
Min.
1)
Clock Input Mid-Point Voltage, CLK and CLK
Clock Input Voltage Level, CLK and CLK
VMP(DC)
VIN(DC)
VID(DC)
0.7 × VDDQ – 0.10
0.7 × VDDQ + 0.10
DDQ + 0.3
VDDQ
V
1)
0.42
0.3
V
V
1)
Clock DC Input Differential Voltage, CLK and
CLK
V
1)2)
Clock AC Input Differential Voltage, CLK and CLK VID(AC)
0.5
VDDQ + 0.5
V
1)3)
AC Differential Crossing Point Input Voltage
VIX(AC)
0.7 × VDDQ – 0.15
0.7 × VDDQ + 0.15
V
1) All voltages referenced to VSS.
2)
VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
3) The value of VIX is expected to equal 0.7 × VDDQ of the transmitting device and must track variations in the DC level of the same.
4.5
Output Test Conditions
FIGURE 13
Output Test Circuit
VDDQ
60 Ohm
Test point
DQ
DQS
Rev. 0.80, 2007-09
25
09132007-07EM-7OYI
QIMONDA [ QIMONDA AG ]
