Internet Data Sheet
HYB15T2G[40/80]2C2F
2-Gbit Dual Die Double-Data-Rate-Two SDRAM
2
Configuration
This chapter contains the chip configuration.
2.1
Configuration for FBGA-63
The chip configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Ball# and BufferType
column are explained in Table 4 and Table 5 respectively.
TABLE 3
Chip Configuration
Ball#
Name
Ball
Type
Buffer
Type
Function
Clock Signals ×4 /×8 Organizations
E8
F8
F2
H1
CK
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Clock Signal CK, CK
Clock Enable
CK
CKE0
CKE1
Control Signals ×4 /×8 Organizations
F7
G7
F3
G8
G9
RAS
CAS
WE
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
CS0
CS1
Chip Select
Address Signals ×4 /×8 Organizations
G2
G3
G1
BA0
BA1
BA2
I
I
I
SSTL
SSTL
SSTL
Bank Address Bus 2:0
Rev. 1.00, 2008-07
6
05082008-A7WT-VELO
QIMONDA [ QIMONDA AG ]
