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HYB15T2G402C2F-25F 参数 Datasheet PDF下载

HYB15T2G402C2F-25F图片预览
型号: HYB15T2G402C2F-25F
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 512MX4, 0.4ns, CMOS, PBGA63, GREEN, PLASTIC, FBGA-63]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 53 页 / 3034 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB15T2G[40/80]2C2F  
2-Gbit Dual Die Double-Data-Rate-Two SDRAM  
1
Overview  
This chapter gives an overview of the 2-Gbit Double-Data-Rate-Two SDRAM product family and describes its main  
characteristics.  
1.1  
Features  
The 2-Gbit Double-Data-Rate-Two SDRAM offers the following key features:  
Power Supply  
Posted CAS by programmable additive latency for better  
command and data bus efficiency  
V
V
V
DD.MIN = VDDQ.MIN =1.45 V  
DD.NOMINAL = VDDQ.NOMINAL =1.5 V  
DD.MAX = VDDQ.MAX =1.9 V  
Off-Chip-Driver impedance adjustment (OCD) and  
On-Die-Termination (ODT) for better signal quality  
Auto-Precharge operation for read and write bursts  
Auto-Refresh, Self-Refresh and power saving Power-  
Down modes  
DRAM organizations with 4,8 data in/outputs  
Double Data Rate architecture:  
– two data transfers per clock cycle  
– eight internal banks for concurrent operation  
Programmable CAS Latency: 3, 4, 5, 6 and 7  
Programmable Burst Length: 4 and 8  
Average Refresh Period 7.8 μs at a TCASE lower  
than 85 °C, 3.9 μs between 85 °C and 95 °C  
Programmable self refresh rate via EMRS2 setting  
Programmable partial array refresh via EMRS2 settings  
DCC enabling via EMRS2 setting  
Differential clock inputs (CK and CK)  
Bi-directional, differential data strobes (DQS and DQS) are  
transmitted / received with data. Edge aligned with read  
data and center-aligned with write data.  
DLL aligns DQ and DQS transitions with clock  
DQS can be disabled for single-ended data strobe  
operation  
Commands entered on each positive clock edge, data and  
data mask are referenced to both edges of DQS  
Data masks (DM) for write data  
Full and reduced Strength Data-Output Drivers  
1KB page size for ×4 and ×8  
Packages: PG-FBGA-63  
RoHS Compliant Products1)  
All Speed grades faster than DDR2–400 comply with  
DDR2–400 timing specifications when run at a clock rate  
of 200 MHz.  
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined  
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,  
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.  
For more information please visit www.qimonda.com/green_products.  
Rev. 1.00, 2008-07  
3
05082008-A7WT-VELO