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HYB15T1G400C2F-3S 参数 Datasheet PDF下载

HYB15T1G400C2F-3S图片预览
型号: HYB15T1G400C2F-3S
PDF下载: 下载PDF文件 查看货源
内容描述: [DDR DRAM, 256MX4, 0.45ns, CMOS, PBGA60, ROHS COMPLIANT, PLASTIC, TFBGA-60]
分类和应用: 时钟动态存储器双倍数据速率内存集成电路
文件页数/大小: 59 页 / 1885 K
品牌: QIMONDA [ QIMONDA AG ]
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Internet Data Sheet  
HYB15T1G[40/80/16]0C2F  
1-Gbit Double-Data-Rate-Two SDRAM  
2
Configuration  
This chapter contains the chip configuration.  
2.1  
Configuration for FBGA-60  
The chip configuration of a DDR2 SDRAM is listed by function in Table 3. The abbreviations used in the Ball# and BufferType  
column are explained in Table 4 and Table 5 respectively.  
TABLE 3  
Chip Configuration  
Ball#  
Name  
Ball  
Type  
Buffer  
Type  
Function  
Clock Signals ×4 /×8 Organizations  
E8  
F8  
F2  
CK  
I
I
I
SSTL  
SSTL  
SSTL  
Clock Signal CK, CK  
Clock Enable  
CK  
CKE  
Control Signals ×4 /×8 Organizations  
F7  
G7  
F3  
G8  
RAS  
CAS  
WE  
I
I
I
I
SSTL  
SSTL  
SSTL  
SSTL  
Row Address Strobe (RAS), Column Address Strobe (CAS), Write  
Enable (WE)  
CS  
Chip Select  
Address Signals ×4 /×8 Organizations  
G2  
G3  
G1  
BA0  
BA1  
BA2  
I
I
I
SSTL  
SSTL  
SSTL  
Bank Address Bus 2:0  
Rev. 1.00, 2008-08  
6
11202007-1NZ2-6U4E