Internet Data Sheet
HYB15T1G[40/80/16]0C2F
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
–25F
–2.5
–3S
Unit
Note
DRAM Speed Grade
DDR2
–800D
5–5–5
–800E
6–6–6
–667D
5–5–5
CAS-RCD-RP latencies
tCK
Max. Clock Frequency
CL3
CL4
CL5
CL6
fCK3
fCK4
fCK5
fCK6
tRCD
tRP
200
266
400
400
12.5
12.5
40
200
266
333
400
15
200
266
333
–
MHz
MHz
MHz
MHz
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
15
15
15
ns
tRAS
tRC
40
40
ns
52.5
15
55
55
ns
1)2)
Precharge-All (8 banks) command period tPREA
17.5
18
ns
1) This tPREA value is the minimum value at which this chip will be functional.
2) Precharge-All command for an 8 bank device will equal to tRP + 1 × tCK or tnRP + 1 × nCK, depending on the speed bin,
where tnRP = RU{ tRP / tCK(avg) } and tRP is the value for a single bank precharge.
1.2
Description
The 1-Gbit DDR2 DRAM is a high-speed Double-Data-Rate-
Two CMOS Synchronous DRAM device containing
1,073,741,824 bits and internally configured as an octal bank
DRAM.
The 1-Gbit device is organized as 32 Mbit ×4 I/O ×8 banks or
16 Mbit ×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1 for performance figures.
A 17 bit address bus for ×4 and ×8 organised components
and a 16 bit address bus for ×16 components is used to
convey row, column and bank address information in a RAS-
CAS multiplexing style.
The device is designed to comply with all DDR2 DRAM key
features:
The DDR2 device operates with VDD.MIN = VDDQ.MIN =1.45 V
and VDD.MAX = VDDQ.MAX =1.9 V power supply. An Auto-
Refresh and Self-Refresh mode is provided along with
various power-saving power-down modes.
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
Rev. 1.00, 2008-08
4
11202007-1NZ2-6U4E
QIMONDA [ QIMONDA AG ]
