Internet Data Sheet
HYB15T1G[40/80/16]0C2F
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 2
Chip Configuration for ×8 Components, FBGA-60, Top View
ꢃ
ꢆ
ꢅ
ꢉ
ꢂ
ꢈ
ꢁ
ꢊ
ꢇ
$
9''
966
9664
9''4
18ꢄ5'46
'46
9664
9664
%
&
'
(
)
*
+
-
'4ꢈ
'0ꢄ5'46
'46
'4ꢁ
9''4
9''4
9''4
9''4
'4ꢃ
'4ꢀ
9664
9664
'4ꢉ
'4ꢅ
'4ꢆ
966'/
5$6
&$6
$ꢆ
'4ꢂ
9''/
95()
966
9''
&.
&.
&6
$ꢀ
&.(
%$ꢀ
$ꢃꢀꢄ$3
$ꢅ
:(
%$ꢃ
$ꢃ
2'7
%$ꢆ
9''
966
$ꢂ
$ꢈ
$ꢉ
966
.
/
$ꢁ
$ꢇ
$ꢃꢃ
1&
$ꢊ
9''
$ꢃꢆ
1&
$ꢃꢅ
0337ꢀꢈꢂꢀ
Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is disabled
3. When enabled, RDQS & RDQS are used as strobe signals during reads.
4. VDDL and VSSDL are power and ground for the DLL. VDDL is connected to VDD on the device. VSSDL is connected to VSS
internally. VDD, VDDQ and VSSQ are isolated on the device.
Rev. 1.00, 2008-08
11
11202007-1NZ2-6U4E
QIMONDA [ QIMONDA AG ]
