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P4C116-10SM 参数 Datasheet PDF下载

P4C116-10SM图片预览
型号: P4C116-10SM
PDF下载: 下载PDF文件 查看货源
内容描述: 超高速2K x 8静态CMOS RAMS [ULTRA HIGH SPEED 2K x 8 STATIC CMOS RAMS]
分类和应用:
文件页数/大小: 14 页 / 239 K
品牌: PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
 浏览型号P4C116-10SM的Datasheet PDF文件第1页浏览型号P4C116-10SM的Datasheet PDF文件第2页浏览型号P4C116-10SM的Datasheet PDF文件第4页浏览型号P4C116-10SM的Datasheet PDF文件第5页浏览型号P4C116-10SM的Datasheet PDF文件第6页浏览型号P4C116-10SM的Datasheet PDF文件第7页浏览型号P4C116-10SM的Datasheet PDF文件第8页浏览型号P4C116-10SM的Datasheet PDF文件第9页  
P4C116/P4C116L  
DATA RETENTION CHARACTERISTICS (P4C116L Military Temperature Only)  
Typ.*  
2.0VCC 3.0V  
Max  
2.0V CC 3.0V  
Symbol  
Parameter  
Test Conditons  
Min  
Unit  
V
=
V
=
V
VDR  
VCC for Data Retention  
Data Retention Current  
2.0  
ICCDR  
tCDR  
10  
15  
600  
900  
µA  
ns  
CE VCC –0.2V,  
VIN VCC –0.2V  
or VIN 0.2V  
Chip Deselect to  
0
Data Retention Time  
§
tR  
Operation Recovery Time  
tRC  
ns  
*TA = +25°C  
§tRC = Read Cycle Time  
This parameter is guaranteed but not tested.  
DATA RETENTION WAVEFORM  
POWER DISSIPATION CHARACTERISTICS VS. SPEED  
Temperature  
Symbol  
Parameter  
Unit  
Range  
–10  
180  
N/A  
–12  
170  
N/A  
–35  
140  
150  
–15  
160  
170  
–20  
155  
160  
–25  
150  
155  
Commercial  
Military  
mA  
mA  
ICC  
Dynamic Operating Current*  
*VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.  
AC ELECTRICAL CHARACTERISTICS—READ CYCLE  
(VCC = 5V ± 10%, All Temperature Ranges)(2)  
–12  
–20  
–25  
–10  
–35  
Max  
Min  
–15  
Sym.  
Parameter  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
Max  
Min  
Max  
Min  
tRC  
Read Cycle Time  
15  
12  
20  
25  
35  
ns  
ns  
ns  
10  
tAA  
tAC  
Address Access Time  
15  
15  
20  
20  
35  
35  
12  
12  
25  
25  
10  
10  
Chip Enable Access Time  
tOH  
tLZ  
Output Hold from Address Change  
Chip Enable to Output in Low Z  
2
2
2
2
2
2
2
2
2
3
2
3
ns  
ns  
tHZ  
Chip Disable to Output in High Z  
Output Enable Low to Data Valid  
10  
15  
5
6
6
8
7
10  
8
10  
15  
20  
ns  
ns  
ns  
tOE  
tOLZ  
tOHZ  
tPU  
tPD  
Output Enable Low to Low Z  
0
0
0
0
0
0
0
0
0
0
0
0
Output Enable High to High Z  
Chip Enable to Power Up Time  
Chip Disable to Power Down  
6
7
12  
20  
8
9
15  
25  
ns  
ns  
ns  
15  
20  
12  
10  
Document # SRAM110 REV A  
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