P4C1024
HIGH SPEED 128K x 8
DUAL CHIP ENABLE
CMOS STATIC RAM
FEATURES
Fast tOE
Automatic Power Down
Packages
—32-Pin 300 mil DIP and SOJ
—32-Pin 400 mil SOJ
—32-Pin 600 mil Ceramic DIP
—32-Pin 400 mil Ceramic DIP
—32-Pin Solder Seal Flatpack
—32-Pin LCC (450 x 550 mil)
—32-Pin LCC (400 x 820 mil) [Two-Sided]
—32-Pin Ceramic SOJ
High Speed (Equal Access and Cycle Times)
— 15/20/25/35 ns (Commercial/Industrial)
— 20/25/35/45/55/70/85/100/120 ns (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
DESCRIPTION
The P4C1024 device provides asynchronous operations
with matching access and cycle times. Memory loca-
tions are specified on address pins A0 to A16. Reading
is accomplished by device selection (CE1 low and CE2
high) and output enabling (OE) while write enable (WE)
remains HIGH. By presenting the address under these
conditions, the data in the addressed memory location
is presented on the data input/output pins. The input/
output pins stay in the HIGH Z state when either CE1 or
OE is HIGH or WE or CE2 is LOW.
The P4C1024 is a 1,048,576-bit high-speed CMOS
static RAM organized as 128Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 15 nanoseconds permit greatly en-
hanced system operating speeds. CMOS is utilized to
reduce power consumption to a low level. The P4C1024
is a member of a family of PACE RAM™ products offer-
ing fast access times.
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (P300, C10, C11),
SOJ (J300, J400, CJ1),
LCC (L1),
SOLDER SEAL
LCC (L6)
FLATPACK (FS-3) SIMILAR
Document # SRAM124 REV C
Revised December 2011
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
