P4C1023/P4C1023L
LOW POWER 128K x 8
SINGLE CHIP ENABLE
CMOS STATIC RAM
FEATURES
Common Data I/O
VCC Current
Three-State Outputs
— Operating: 35mA
— CMOS Standby: 100µA
Access Times
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—55/70 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
—32-Pin 400 or 600 mil Ceramic DIP
—32-Pin Ceramic SOJ
DESCRIPTION
The P4C1023L is a 1 Megabit low power CMOS static
RAM organized as 128K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
locations are specified on address pinsA0 toA16. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1023L is packaged in a 32-pin 400 or 600 mil
ceramic DIP and in a 32-pin ceramic SOJ.
The P4C1023L device provides asynchronous opera-
tion with matching access and cycle times. Memory
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (C10, C11), CERAMIC SOJ (CJ1)
TOP VIEW
Document # SRAM126 REV OR
Revised October 2005
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
