PACE1754
PIN FUNCTIONS (Continued)
Symbol
R/W
Name
Description
Read or Write
An input qualifier indicating the nature of the current bus cycle, either
Read (1) or Write (0).
RESET
External Reset
An active LOW input used to initialize the device's hardware.
TEST ON
System Test Enable
An active LOW input used to enable the execution of the System
Test built into the device, immediately after completion of the P1754
initialization and before fetching any instruction from the user
program.
TEST END
STRT ROM
System Test End
Start Up ROM
An active HIGH output indicating whether the system test in the
device has been completed. Whenever the system test is disabled
by the TEST ON signal, the TEST END output will be at a logical "1"
immediately after RESET is removed.
An output following the execution of the ESUR and DSUR, I/O
commands as defined in MIL-STD-1750A. It will be at the logical "1"
level after executing ESUR and at the logical "0" level after executing
DSUR. Initially, it defaults to a logical "1".
RDYD
Ready Data
An active HIGH output to be connected to the P1750A/AE CPU input
to control the bus cycle termination.
EX RDY
EX RDY1
External Ready Data
External Ready Data
Memory Parity Error
An active HIGH input which at logical "0" overrides the internal
RDYD generation and forces it to a logical "0".
An active LOW input which at logical "1" overrides the internal RDYD
generation and forces it to a logical "0".
ME PA ER/
RAM DIS
An active LOW output indicating a parity error when reading from
memory. It becomes an active HIGH output called RAM DISABLE
for handshaking with the P1753 MMU when the device is
programmed to support EDAC.
EX AD ER/
SING ERR
Illegal Address Error
An active LOW output indicating an illegal address error when
referencing memory or I/O. It becomes an active HIGH output called
SINGLE ERROR for handshaking with the P1753 MMU when the
device is programmed to support EDAC.
TC
Terminal Count
An active HIGH output indicating a Bus time out or a watchdog
trigger.
SC –SC
System Configuration
Inputs (for case outlines U, Y, and Z only) which are buffered onto
0
4
IB –IB when executing an I/O read from I/O address 8410 (hex),
0
4
system configuration.
GND
Ground
0 volts system ground.
5 volts ± 10% power supply.
V
CC
Power Supply
Case U: Leaded Chip Carrier with Unformed Leads
Case Y: Leaded Chip Carrier with Gull-Wing Leads
Case Z: Pin Grid Array
Do c um e nt # MICRO-5 REV C
Pa g e 13 o f 20
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
