P1750AE/SOS
SIGNAL DESCRIPTIONS (Continued)
BUSCONTROL
Mnemonic
Name
Description
D/l
Data or instruction
An output signal that indicates whether the current bus cycle access is
for Data (HIGH) or Instruction (LOW). It is three-state during bus cycles
not assigned to this CPU. This line can be used as an additional
memory address bit for systems that require separate data and program
memory.
R/W
Readorwrite
An output signal that indicates direction of data flow with respect to the
current bus master. A HIGH indicates a read or input operation and a
LOW indicates a write or output operation. The signal is three-state
during bus cycles not assigned to this CPU.
M/IO
Memory or I/O
Addressstrobe
Addressready
Datastrobe
An output signal that indicates whether the current bus cycle is memory
(HIGH) or I/O (LOW). This signal is three-state during bus cycles not
assigned to this CPU.
STRBA
RDYA
STRBD
RDYD
An active HIGH output that can be used to externally latch the memory
or I/O address at the high-to-low transition of the strobe. The signal is
three-state during bus cycles not assigned to this CPU.
An active HIGH input that can be used to extend the address phase of a
bus cycle. When RDYA is not active wait states are inserted by the
device to accommodate slower memory or I/O devices.
An active LOW output that can be used to strobe data in memory and
XIO cycles. This signal is three-state during bus cycles not assigned to
this CPU.
Dataready
An active HIGH input that extends the data phase of a bus cycle. When
RDYD is not active, wait states are inserted by the device to
accommodate slower memory or I/O devlces.
INFORMATION BUS
Mnemonic Name
IB - IB
Description
Information bus
A bidirectional time-multiplexed address/data bus that is three-state
0
15
during bus cycles not assigned to this CPU. IB is the most significant
0
bit.
STATUS BUS
Mnemonic
Name
Description
AK - AK
Access key
Outputs used to match the access lock in the MMU for memory
accesses (a mismatch will cause the MMU to pull the MEM PRT ER
signal LOW), and also indicates processor state (PS). Privileged
instructions can be executed with PS = 0 only. These signals are
three-state during bus cycles not assigned to this CPU.
0
3
AS - AS
Address state
Outputs that select the page register group in the MMU. It is three-
state during bus cycles not assigned to this CPU. [These outputs
together with D/l can be used to expand the device direct addressing
space to 4 MBytes, in a nonprotected mode (no MMU)]. However,
using this addressing mode may produce situations not specified in
MIL-STD-1750A.
0
3
Do c um e nt # MICRO-7 REV B
Pa g e 16 o f 22
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