May 2008
rev 0.5
Switching Characteristics for ASM3P622S00B/E
Parameter
Input Frequency
Output Frequency
Duty Cycle
6,7
= (t
2
/ t
1
) * 100
Output Rise Time
7, 8
Output Fall Time
7, 8
Output-to-output skew
7, 8
Delay, CLKIN Rising Edge to
CLKOUT Rising Edge
8
ASM3P622S00B/E
Test Conditions
30pF load
Measured at VDD/2
Measured between 0.8V and 2.0V
Measured between 2.0V and 0.8V
All outputs equally loaded with SSOFF
Measured at VDD /2 with SSOFF
Measured at VDD/2 on the CLKOUT pins
of the device
Loaded outputs
< 8MHz
> 8MHz
Min
4
4
40
Typ
Max
20
20
Unit
MHz
MHz
%
nS
nS
pS
pS
pS
nS
pS
mS
50
60
2.5
2.5
250
±350
700
±1.6
±200
1.0
Device-to-Device Skew
8
Cycle-to-Cycle Jitter
7, 8
PLL Lock Time
8
Stable power supply, valid clock presented
on CLKIN pin
Note: 7. All parameters specified with 30pF loaded outputs.
8. Parameter is guaranteed by design and characterization. Not 100% tested in production
Switching Waveforms
Duty Cycle Timing
t
1
t
2
V
DD
/2
OUTPUT
V
DD
/2
V
DD
/2
All Outputs Rise/Fall Time
2V
0.8V
2V
0.8V
3.3V
OUTPUT
t
3
t
4
0V
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
