May 2008
rev 0.5
Pin Configuration for ASM3P622S00E
ASM3P622S00B/E
CLKIN
CLKOUT1
VDD
SS%
GND
CLKOUT2
CLKOUT3
1
2
3
4
16
15
14
13
CLKOUT
CLKOUT7
CLKOUT6
VDD
GND
CLKOUT5
CLKOUT4
SSON
ASM3P622S00E
5
6
7
12
11
10
9
DLY_CTRL
8
Pin Description for ASM3P622S00E
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
CLKIN
1
CLKOUT1
2
V
DD
SS%
3
GND
CLKOUT2
2
CLKOUT3
2
DLY_CTRL
SSON
3
CLKOUT4
2
CLKOUT5
2
GND
V
DD
CLKOUT6
2
CLKOUT7
2
CLKOUT
2
Type
I
O
P
I
P
O
O
O
I
O
O
P
P
O
O
O
Buffered clock output
4
3.3V supply
Description
External reference Clock input, 5V tolerant input
Spread Spectrum Selection. Refer
Spread Spectrum Control and Input-Output Skew
Table. Has an internal pull up resistor
Ground
Buffered clock output
4
Buffered clock output
4
External Input-Output Delay control
.
Spread Spectrum enable and disable option. When SSON is HIGH, the spread
spectrum is enabled and when LOW, it turns off the spread spectrum. Has an internal
pull up resistor
Buffered clock output
4
Buffered clock output
4
Ground
3.3V supply
Buffered clock output
4
Buffered clock output
4
Buffered clock output
4
Notes: 1.Weak pull down
2. Weak pull-down on all outputs
3. Weak pull-up on these Inputs
4. Buffered clock output is Timing-Safe™
Low Frequency Timing-Safe™ Peak EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
