November 2006
rev 0.3
Table 9. AC Characteristics
(VCC = VCCA = VCCB = VCCC = 2.5V ± 5%, T
A
= -40 to +85°C)
1
Symbol
f
ref
f
MAX
V
PP
V
CMR3
t
P
,
REF
t
r
, t
f
t
PLH
t
PHL
t
PLZ
,
HZ
t
PZL
,
LZ
Characteristics
Input Frequency
Maximum Output Frequency
Peak-to-peak input voltage
Common Mode Range
Reference Input Pulse Width
PCLK Input Rise/Fall Time
Propagation delay
Output Disable Time
Output Enable Time
Within one bank
t
sk(O)
Output-to-output
Skew
Any output bank, same output
divider
Any output, Any output divider
t
sk(PP)
t
SK(P)
DC
Q
t
r
, t
f
Device-to-device Skew
Output pulse skew
5
Output Duty Cycle
Output Rise/Fall Time
÷1 or ÷2 output
45
0.1
50
PCLK to any Q
PCLK to any Q
2.6
2.6
÷1 output
÷2 output
PCLK
PCLK
Min
0
0
0
500
1.1
1.4
1.0
5.6
5.5
10
10
150
200
350
3.0
200
55
1.0
4
ASM2I99456
Typ
Max
250
2
250
2
125
1000
VCC-0.7
Unit
MHz
MHz
MHz
mV
V
nS
nS
nS
nS
nS
nS
pS
pS
pS
nS
pS
%
nS
Condition
FSELx=0
FSELx=1
LVPECL
LVPECL
0.7 to 1.7V
DC
REF
= 50%
0.6 to 1.8V
Note: 1 AC characteristics apply for parallel output termination of 50Ω
to V
TT
.
2 The ASM2I99456 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250 MHz.
3 V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
CMR
range and the input
swing lies within the V
PP
(AC) specification.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
- t
PHL
|.
Table 10. AC Characteristics
(VCC = 3.3V ± 5%, VCCA = VCCB = VCCC = 2.5V ± 5% or 3.3V ± 5%,T
A
= -40 to +85°C)
,1,2
Symbol
Characteristics
Within one bank
t
sk(O)
Output-to-output
Skew
Any output bank, same output
divider
Any output, Any output divider
t
sk(PP)
t
PLH,HL
t
SK(P)
DC
Q
Device-to-device Skew
Propagation delay
Output pulse skew
3
Output Duty Cycle
÷1 or ÷2 output
45
50
PCLK to any Q
Min
Typ
Max
150
250
350
2.5
See 3.3V table
250
55
pS
%
DC
REF
= 50%
Unit
pS
pS
pS
nS
Condition
Note: 1 AC characteristics apply for parallel output termination of 50Ω
to V
TT
.
2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
3 Output pulse skew is the absolute difference of the propagation delay times: | t
PLH
- t
PHL
|.
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
