November 2006
rev 0.3
Block Diagram
Bank A
PCLK
PCLK
VCC/2
25K
Bank B
0
1
25K
CLK
CLK÷ 2
0
1
ASM2I99456
QA0
QA1
QA2
QB0
QB1
QB2
FSELA
25K
FSELB
25K
FSELC
MR/OE
0
1
25K
25K
Bank C
QC0
QC1
QC2
QC3
ASM2I99456 Logic Diagram
Pin Configuration
VCCC
VCCB
VCCB
GND
GND
QB0
QB1
QB2
VCCB is internally connected to VCC
24
VCCA
QA2
GND
QA1
VCCA
QA0
GND
MR/OE
25
26
27
28
29
30
31
32
1
23
22
21
20
19
18
17
16
15
14
QC3
GND
QC2
VCCC
QC1
GND
QC0
VCCC
ASM2I99456
13
12
11
10
9
2
3
4
5
6
7
8
PECL_CLK
PCL_CLK
FSELB
FSELA
FSELC
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
GND
NC
VCC
2 of 14