November 2006
rev 0.3
Applications Information
Driving Transmission Lines
The ASM2I99456 clock driver was designed to drive high
speed signals in a terminated transmission line
environment. To provide the optimum flexibility to the
user the output drivers were designed to exhibit the
lowest impedance possible. With an output impedance of
less than 20Ω the drivers can drive either parallel or
series terminated transmission lines. In most high
performance clock networks point-to-point distribution of
signals is the method of choice. In a point-to-point
scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique
terminates the signal at the end of the line with a
50Ω resistance to V
CC
÷2.
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the ASM2I99456 clock driver. For the series
terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated
lines. Figure 1. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken
to its extreme the fanout of the ASM2I99456 clock driver
is effectively doubled due to its capability to drive multiple
lines.
ASM2I99456
OUTPUT BUFFER
14Ω
R
S
=36Ω
Z
0
=50Ω
ASM2I99456
impedance mismatch seen looking into the driver. The
parallel combination of the 36Ω series resistor plus the
output impedance does not match the parallel
combination of the line impedances. The voltage wave
launched down the two lines will equal:
V
L
= V
S
( Z
0
÷ (R
S
+R
0
+Z
0
))
Z
0
= 50Ω || 50Ω
R
S
= 36Ω || 36Ω
R
0
= 14Ω
V
L
= 3.0 ( 25 ÷ (18+14+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.5V. It will then increment
towards the quiescent 3.0V in steps separated by one
round trip delay (in this case 4.0nS).
3.0
2.5
VOLTAGE (V)
2.0
In
1.5
1.0
0.5
0
2
4
6
8
10
12
14
TIME (nS)
OutA
t
D
= 3.8956
OutB
t
D
= 3.9386
ASM2I99456
OUTPUT BUFFER
14Ω
R
S
=36Ω
Z
0
=50Ω
Figure 2. Single versus Dual Waveforms
Z
0
=50Ω
R
S
=36Ω
Figure 1. Single versus Dual Transmission Lines
The waveform plots in Figure 2. “Single versus Dual Line
Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both
cases the drive capability of the ASM2I99456 output
buffer is more than sufficient to drive 50Ω transmission
lines on the incident edge. Note from the delay
measurements in the simulations a delta of only 43pS
exists between the two differently loaded outputs. This
suggests that the dual line driving need not be used
exclusively to maintain the tight output-to-output skew of
the ASM2I99456. The output waveform in Figure 2.
“Single versus Dual Line Termination Waveforms” shows
a step in the waveform, this step is caused by the
Since this step is well above the threshold region it will
not cause any false clock triggering, however designers
may be uncomfortable with unwanted reflections on the
line. To better match the impedances when driving
multiple lines the situation in Figure 3. “Optimized Dual
Line Termination” should be used. In this case the series
terminating resistors are reduced such that when the
parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
ASM2I99456
OUTPUT BUFFER
14Ω
R
S
=22Ω
R
S
=22Ω
Z
0
=50Ω
Z
0
=50Ω
14Ω + 22Ω
||
22Ω = 50Ω
||
50Ω
25Ω = 25Ω
3.3V/2.5V LVCMOS Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
