January 2006
rev 0.2
2.5V
1.25V
INPUT
t
PLH
t
PLHL 1
OV
ASM2P20807A
V
OH
1.25 V
OUTPUT 1
t
SK(O)
t
SK(O)
V
OL
V
OH
1.25 V
OUTPUT 2
t
PLH2
t
PHL2
V
OL
t
SK(O)
=[ t
PLH2
– t
PLH 1
] or [t
PHL2 -
t
PHL1
]
Output Skew - t
SK(O)
2.5V
1.25V
INPUT
t
PLH 1
t
PLHL
OV
1
V
OH
1.25 V
DEVICE 1 OUTPUT
t
SK(t)
t
SK(t)
V
OL
V
OH
1.25 V
DEVICE 2 OUTPUT
t
PLH2
t
PHL2
V
OL
DEVICE 2 OUTPUT
t
SK(t)
=[ t
PLH2
– t
PLH 1
] or [t
PHL2 -
t
PHL1
]
NOTE: Device 1 and device 2 are same package type and speed grade.
Part-to-Part Skew - t
SK(PP)
Test Conditions
Symbol
C
L
VCC = 2.5V ±0.2V
22
1
Unit
pF
Ω
nS
12
2
R
T
t
R
/ t
F
Z
OUT
of pulse generator
1.25
1
1.2
2
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to ZOUT of the Pulse Generator.
t
R
/ t
F
= Rise/Fall time of the input stimulus from the Pulse Generator.
NOTES:
1. Test conditions at 100MHz.
2. Test conditions at 150MHz.
2.5V CMOS 1-TO-10 CLOCK DRIVER
Notice: The information in this document is subject to change without notice.
7 of 12
PULSECORE [ PulseCore Semiconductor ]
