PE64906
Product Specification
Serial Interface Operation and Sharing
The PE64906 is controlled by a three wire SPI-compatible
interface. As shown in
Figure 11,
the serial master
initiates the start of a telegram by driving the SEN (Serial
Enable) line high. Each bit of the 8-bit telegram is clocked
in on the rising edge of the SCL (Serial Clock) line. SDA
bits are clocked by most significant bit (MSB) first, as
shown in
Table 5
and
Figure 11.
Transactions on SDA
(Serial Data) are allowed on the falling edge of SCL. The
DTC activates the data on the falling edge of SEN. The
DTC does not count how many bits are clocked and only
maintains the last 8 bits it received.
More than 1 DTC can be controlled by one interface by
utilizing a dedicated enable (SEN) line for each DTC.
SDA, SCL, and V
DD
lines may be shared as shown in
Figure 12.
Dedicated SEN lines act as a chip select such
that each DTC will only respond to serial transactions
intended for them. This makes each DTC change states
sequentially as they are programmed.
Alternatively, a dedicated SDA line with common SEN
can be used. This allows all DTCs to change states
simultaneously, but requires all DTCs to be programmed
even if the state is not changed.
Figure 11. Serial Interface Timing Diagram (oscilloscope view)
t
EOW
t
ESU
t
DSU
t
DHD
t
R
t
F
t
SCL
t
SCLH
t
SCLL
t
EHD
SEN
SCL
SDA
b0
b7
b6
b5
b4
b3
b2
b1
b0
DTC Data
D
m-2
<7:0>
D
m-1
<7:0>
D
m
<7:0>
Table 5. Register Map
b7
0
1
Figure 12. Recommended Bus sharing
b3
d3
b6
0
1
b5
STB
2
b4
d4
b2
d2
b1
d1
b0
d0
DTC 1
RF+
V
DD
SDA
SCL
SEN1
SEN2
V
DD
SDA
SCL
SEN
DGND
RF-
DTC 2
RF+
V
DD
SDA
SCL
SEN
DGND
RF-
GND
GND
MSB (first in)
Notes:
LSB (last in)
1. These bits are reserved and must be written to 0 for proper operation
2. The DTC is active when low (set to 0) and in low-current stand-by
mode when high (set to 1)
Table 6. Serial Interface Timing Characteristics
V
DD
= 2.75V, -40°C < T
A
< +85°C, unless otherwise specified
Symbol
t
SCL
t
SCLL
t
SCLH
t
R
t
F
t
ESU
t
EHD
t
DSU
t
DHD
t
EOW
SCL low time
SCL high time
SCL, SDA, SEN rise time
SCL, SDA, SEN fall time
SEN rising edge to SCL rising edge
SCL rising edge to SEN falling edge
SDA valid to SCL rising edge
SDA valid after SCL rising edge
SEN falling edge to SEN rising edge
19.2
19.2
13.2
13.2
38.4
Parameter
Serial clock period
Min
38.4
13.2
13.2
6.5
6.5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document No. DOC-30114-3
©2013 Peregrine Semiconductor Corp. All rights reserved.
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