PE43601
Product Specification
Figure 20. Serial-Addressable Timing Diagram
Bits can either be set to logic high or logic low
D[6] and D[7] must be set to logic low
DI[5:0]
T
DISU
T
DIH
ADD[2:0]
P/S
VALID
T
ASU
T
AIH
T
PSSU
T
PSIH
SI
T
SISU
T
SIH
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
A[0]
A[1]
A[2]
CLK
T
CLKL
T
CLKH
T
LESU
LE
T
LEPW
T
PD
VALID
DO[6:0]
Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram
P/S
T
PSSU
T
PSIH
VALID
T
DISU
T
DIH
DI[5:0]
LE
T
LEPW
DO[5:0]
T
DIPD
VALID
T
PD
Table 11. Serial-Addressable Interface
AC Characteristics
V
DD
= 3.3 or 5.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
F
CLK
T
CLKH
T
CLKL
T
LESU
T
LEPW
T
SISU
T
SIH
T
DISU
T
DIH
T
ASU
T
AH
T
PSSU
T
PSH
T
PD
Table 12. Parallel and Direct Interface
AC Characteristics
V
DD
= 3.3 or 5.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
T
LEPW
T
DISU
T
DIH
T
PSSU
Parameter
Serial clock frequency
Serial clock HIGH time
Serial clock LOW time
Last serial clock rising edge
setup time to Latch Enable
rising edge
Latch Enable min. pulse width
Serial data setup time
Serial data hold time
Parallel data setup time
Parallel data hold time
Address setup time
Address hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay (internal)
Min
-
30
30
10
30
10
10
100
100
100
100
100
100
-
Max
10
-
-
-
-
-
-
-
-
-
-
-
-
10
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Latch Enable minimum
pulse width
Parallel data setup time
Parallel data hold time
Parallel/Serial setup time
Parallel/Serial hold time
Digital register delay
(internal)
Digital register delay
(internal, direct mode only)
Min
30
100
100
100
100
-
-
Max
-
-
-
-
-
10
5
Unit
ns
ns
ns
ns
ns
ns
ns
T
PSIH
T
PD
T
DIPD
Document No. 70-0253-05
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©2008-2009 Peregrine Semiconductor Corp. All rights reserved.
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