PE43601
Product Specification
Table 5. Control Voltage
State
Low
High
Table 8. Address Word Truth Table
Bias Condition
Address Word
A7
(MSB)
X
X
X
X
0 to +1.0 Vdc at 2
µA
(typ)
+2.6 to +5 Vdc at 10
µA
(typ)
A6
X
X
X
X
X
X
X
X
A5
X
X
X
X
X
X
X
X
A4
X
X
X
X
X
X
X
X
A3
X
X
X
X
X
X
X
X
A2
L
L
L
L
H
H
H
H
A1
L
L
H
H
L
L
H
H
A0
L
H
L
H
L
H
L
H
Address
Setting
000
001
010
011
100
101
110
111
Table 6. Latch and Clock Specifications
Latch Enable
X
↑
X
X
X
X
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
Table 7. Parallel Truth Table
Parallel Control Setting
D5
L
L
L
L
L
L
H
H
Table 9. Serial Attenuation Word Truth Table
Attenuation Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
15.75 dB
Attenuation Word
D7
L
L
L
L
L
L
L
L
D4
L
L
L
L
L
H
L
H
D3
L
L
L
L
H
L
L
H
D2
L
L
L
H
L
L
L
H
D1
L
L
H
L
L
L
L
H
D0
L
H
L
L
L
L
L
H
D6
L
L
L
L
L
L
L
L
D5
L
L
L
L
L
L
H
H
D4
L
L
L
L
L
H
L
H
D3
L
L
L
L
H
L
L
H
D2
L
L
L
H
L
L
L
H
D1
L
L
H
L
L
L
L
H
D0
(LSB)
L
H
L
L
L
L
L
H
Attenuation
Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
15.75 dB
Table 10. Serial-Addressable Register Map
Bits can either be set to logic high or logic low
MSB (last in)
Q15
A7
Q14
A6
Q13
A5
Q12
A4
Q11
A3
Q10
A2
D6 and D7 must be set to logic low
LSB (first in)
Q9
A1
Q8
A0
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
Address Word
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 12.75 dB state
at address 3:
Address Word: XXXXX011
Attenuation Word: Multiply by 4 and convert to binary
→
4 * 12.75 dB
→
51
→
00110011
Serial Input: XXXXX01100110011
Document No. 70-0253-05
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