PE43404
Product Specification
Figure 18. Serial Interface Timing Diagram
LE
Table 7. 4-Bit Attenuator Serial Programming
Register Map
Clock
B5
0
B4
C8
B3
C4
B2
C2
B1
C1
B0
0
Data
MSB
LSB
↑
MSB (first in)
t
LESUP
t
LEPW
↑
LSB (last in)
t
SDSUP
t
SDHLD
Note: The start bit (B5) and stop bit (B0) must always be low to
prevent an unknown state in the device .
Figure 19. Parallel Interface Timing Diagram
LE
Parallel Data
C8:C1
t
PDSUP
t
LEPW
t
PDHLD
Table 8. Serial Interface AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
LESUP
t
LEPW
t
SDSUP
t
SDHLD
Note:
Table 9. Parallel Interface AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
t
LEPW
t
PDSUP
t
PDHLD
Parameter
Serial data clock
frequency (Note 1)
Serial clock HIGH time
Serial clock LOW time
LE set-up time after last
clock falling edge
LE minimum pulse width
Serial data set-up time
before clock rising edge
Serial data hold time
after clock falling edge
Min
Max
10
Unit
MHz
ns
ns
ns
ns
ns
ns
Parameter
LE minimum pulse width
Data set-up time before
rising edge of LE
Data hold time after
falling edge of LE
Min
10
10
10
Max
--
--
--
Unit
ns
ns
ns
30
30
10
30
10
10
f
Clk
is verified during the functional pattern test. Serial
programming sections of the functional pattern are clocked
at 10 MHz to verify fclk specification.
©2008 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0258-02
│
UltraCMOS™ RFIC Solutions
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