PE43404
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit was designed to
ease customer evaluation of the PE43404 DSA.
J9 is used in conjunction with the supplied DC cable to
supply V
DD
, GND, and –V
DD
. If use of the internal
negative voltage generator is desired, then connect –
V
DD
(black banana plug) to ground. If an external –V
DD
is desired, then apply -3V.
J1 should be connected to the LPT1 port of a PC with
the supplied control cable. The evaluation software is
written to operate the DSA in serial mode, so switch 7
(P/S) on the DIP switch SW1 should be ON with all
other switches off. Using the software, enable or
disable each attenuation setting to the desired
combined attenuation. The software automatically
programs the DSA each time an attenuation state is
enabled or disabled.
Note: Jumper J6 supplies power to the evaluation
board support circuits.
To evaluate the Power Up options, first disconnect the
control cable from the evaluation board. The control
cable must be removed to prevent the PC port from
biasing the control pins.
During power up with P/S=1 high and LE=1, the default
power-up signal attenuation is set to the value present
on the four control bits on the four parallel data inputs
(C1 to C8). This allows any one of the 32 attenuation
settings to be specified as the power-up state.
During power up with P/S=0 high and LE=0, the control
bits are automatically set to one of two possible values
presented through the PUP interface. These two
values are selected by the power-up control bit, PUP2,
as shown in Table 6.
Pins 1 and 7 are open and may be connected to any
bias.
J18
SMA
Z=75 Ohm
1
R25
DATA
R23
0 OHM
10K
CLK
LE
Figure 4. Evaluation Board Layout
Peregrine Specification 101-0112
Figure 5. Evaluation Board Schematic
Peregrine Specification 102-0142
C1
C
2
18
17
C2
20
19
G
ND
C1
C4
16
C
4
N/C
1
2
3
4
5
GND
N/C
C8
15
14
13
12
11
C8
R24 0 OHM
PS
-VDD
Z=75 Ohm
1
J19
SMA
RFIN
DATA
CLK
U4
MLPQ4X4
RFOUT
PS
VNEG
J20
SUPPLY
VDD
4
3
2
1
2
or GND
PUP1
6
7
8
PUP2
VDD
LE
9
10
VDD_D
GND
GND
C14
100pF
C12
0.1µF
VDD
PUP1
Note: Resistor on pin 3 is required and
should be placed as close to the part
as possible to avoid package
resonance and meet error
specifications over frequency.
P
UP2
C10
100pF
C9
0.1µF
Document No. 70-0258-02
│
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©2008 Peregrine Semiconductor Corp. All rights reserved.
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