PE42556
Product Specification
Figure 3. Bump Configuration (Bumps Up)
Flip Chip Packaging
Vdd
CTRL
Vss
Table 4. Absolute Maximum Ratings
Parameter/Conditions
Power supply voltage
Voltage on any input except
V
I
for CTRL and LS inputs
Voltage on CTRL input
V
CTRL
V
LS
Voltage on LS input
T
ST
Storage temperature range
T
OP
Operating temperature range
9 kHz
≤
1 MHz
5
P
IN
(50Ω)
1 MHz
≤
13.5 GHz
ESD voltage (HBM)
6
V
ESD
ESD voltage (Machine Model)
Notes:
Symbol
V
DD
Min
-0.3
-0.3
11
LS
12
D-GND
1
D-GND
10
GND
13
DGND
2
GND
9
RF1
14
3
RF2
-65
-40
8
GND
RFC
4
GND
7
6
5
Max
4.0
V
DD
+
0.3
4.0
4.0
150
85
Fig. 4,5
30
4000
300
Units
V
V
V
V
°C
°C
dBm
dBm
V
V
5. Please consult
Figures 4
and
5
(low-frequency graphs) for
recommended low-frequency operating power level.
6. Human Body Model (HBM, MIL_STD 883 Method 3015.7)
Table 2. Bump Descriptions
Bump
No.
1
2, 13, 14
3, 5, 7, 9
4
6
8
10
11
12
Bump
Name
V
SS
D-GND
GND
RF2
RFC
RF1
LS
V
DD
CTRL
Description
Negative supply voltage or GND
connection (Note 3)
Digital Ground
Ground
RF Port 2
RF Common
RF Port 1
Logic Select - Used to determine the
definition for the CTRL pin (see
Table 5)
Nominal 3.3V supply connection
CMOS logic level
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted to
the limits in the Operating Ranges table. Operation
between operating range maximum and absolute
maximum for extended periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other ESD-
sensitive devices. Although this device contains
circuitry to protect it from damage due to ESD,
precautions should be taken to avoid exceeding the
rating specified.
®
Note: 3. Use VSS (bump 1, VSS = -VDD) to bypass and disable internal
negative voltage generator. Connect VSS (bump 1) to GND (VSS = 0V) to
enable internal negative voltage generator.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
®
Table 3. Operating Ranges
Parameter
V
DD
Positive Power Supply
Voltage
V
DD
Negative Power Supply
Voltage
I
DD
Power Supply Current
(V
ss
= -3.3V, V
DD
= 3.0 to
3.6V, -40 to +85 °C)
I
DD
Power Supply Current
(V
ss
= 0V, V
DD
= 3.0 to 3.6V,
-40 to +85 °C)
I
SS
Negative Power Supply
Current
(V
ss
= -3.3V, V
DD
= 3.0 to
3.6V, -40 to +85 °C)
Control Voltage High
Control Voltage Low
P
IN
RF Power In
4
(50Ω):
9 kHz
≤
1 MHz
1 MHz
≤
13.5 GHz
0.7xV
DD
0.3xV
DD
Fig. 4,5
30
Table 5. Control Logic Truth Table
Typ
3.3
-3.3
8.0
Min
3.0
-3.6
Max
3.6
-3.0
12.5
Units
V
V
μA
LS
0
0
1
1
CTRL
0
1
0
1
RFC-RF1
off
on
on
off
RFC-RF2
on
off
off
on
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
21.5
29.0
μA
Spurious Performance
The typical spurious performance of the PE42556 is
-116 dBm when VSS = 0V (bump 1 = GND). If further
improvement is desired, the internal negative voltage
generator can be disabled by setting VSS = -VDD.
-18.0
-24.0
μA
V
V
dBm
dBm
Switching Frequency
The PE42556 has a maximum 25 kHz switching rate
when the internal negative voltage generator is used
(bump1 = GND). The rate at which the PE42556 can
be switched is only limited to the switching time
(Table
1)
if an external negative supply is provided
(bump1 = VSS).
©2009-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 3 of 10
Note: 4. Please consult Figures 4 and 5 (low-frequency graphs) for recommended
low-frequency operating power level.
Document No. 70-0289-06
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