TOP412/414
TOPSwitch Family Functional Description (cont.)
The first time VC reaches the upper threshold, the high-voltage
current source is turned off and the PWM modulator and output
transistorareactivated, asshowninFigure5(a). Duringnormal
operation (when the output voltage is regulated) feedback
control current supplies the VC supply current. The shunt
regulator keeps VC at typically 5.7 V by shunting CONTROL
pin feedback current exceeding the required DC supply current
through the PWM error signal sense resistor RE. The low
dynamic impedance of this pin (ZC) sets the gain of the error
amplifier when used in a primary feedback configuration. The
dynamic impedance of the CONTROL pin together with the
external resistance and capacitance determines the control loop
compensation of the power system.
typical corner frequency of 7 kHz to reduce the effect of
switching noise. The filtered error signal is compared with the
internal oscillator sawtooth waveform to generate the duty
cycle waveform. As the control current increases, the duty
cycle decreases. A clock signal from the oscillator sets a latch
whichturnsontheoutputMOSFET. Thepulsewidthmodulator
resetsthelatch,turningofftheoutputMOSFET. Themaximum
duty cycle is set by the symmetry of the internal oscillator. The
modulator has a minimum ON-time to keep the current
consumption of the TOPSwitch independent of the error signal.
NotethataminimumcurrentmustbedrivenintotheCONTROL
pin before the duty cycle begins to change.
Gate Driver
If the CONTROL pins total external capacitance (CT) should
discharge to the lower threshold, the output MOSFET is turned
off and the control circuit is placed in a low-current standby
mode. Thehigh-voltagecurrentsourceisturnedonandcharges
the external capacitance again. Charging current is shown with
a negative polarity and discharging current is shown with a
positive polarity in Figure 6. The hysteretic auto-restart
comparator keeps VC within a window of typically 4.7 to 5.7 V
by turning the high-voltage current source on and off as shown
in Figure 5(b). The auto-restart circuit has a divide-by-8
counter which prevents the output MOSFET from turning on
again until eight discharge-charge cycles have elapsed. The
counter effectively limits TOPSwitch power dissipation by
reducing the auto-restart duty cycle to typically 5%. Auto-
restartcontinuestocycleuntiloutputvoltageregulationisagain
achieved.
The gate driver is designed to turn the output MOSFET on at a
controlled rate to minimize common-mode EMI. The gate
drive current is trimmed for improved accuracy.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifierinprimaryfeedbackapplications. Theshuntregulator
voltageisaccuratelyderivedfromthetemperaturecompensated
bandgap reference. The gain of the error amplifier is set by the
CONTROL pin dynamic impedance. The CONTROL pin
clamps external circuit signals to the VC voltage level. The
CONTROL pin current in excess of the supply current is
separated by the shunt regulator and flows through RE as the
error signal.
Cycle-By-Cycle Current Limit
The cycle by cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
limit comparator compares the output MOSFET ON-state
drain-source voltage, VDS(ON), with a threshold voltage. High
drain current causes VDS(ON) to exceed the threshold voltage and
turns the output MOSFET off until the start of the next clock
cycle. The current limit comparator threshold voltage is
temperaturecompensatedtominimizevariationoftheeffective
peak current limit due to temperature related changes in output
Bandgap Reference
All critical TOPSwitch internal voltages are derived from a
temperature-compensated bandgap reference. This reference
is also used to generate a temperature-compensated current
sourcewhichistrimmedtoaccuratelysettheoscillatorfrequency
and MOSFET gate drive current.
Oscillator
The internal oscillator linearly charges and discharges the
internal capacitance between two voltage levels to create a
sawtoothwaveformforthepulsewidthmodulator. Theoscillator
setsthepulsewidthmodulator/currentlimitlatchatthebeginning
of each cycle. The nominal frequency of 120 kHz was chosen
to minimize EMI and maximize efficiency in power supply
applications. Trimming of the current reference improves the
frequency accuracy.
MOSFET RDS(ON).
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that current
spikescausedbyprimary-sidecapacitancesandsecondary-side
rectifier reverse recovery time will not cause premature
termination of the switching pulse.
Pulse Width Modulator
Shutdown/Auto-restart
The pulse width modulator implements a voltage-mode control
loopbydrivingtheoutputMOSFETwithadutycycleinversely
proportional to the current flowing into the CONTROL pin.
The error signal across RE is filtered by an RC network with a
To minimize TOPSwitch power dissipation, the shutdown/
auto-restart circuit turns the power supply on and off at a duty
cycle of typically 5% if an out of regulation condition persists.
Loss of regulation interrupts the external current into the
A
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POWERINT [ Power Integrations ]
